Investigating SNNs for Identifying and Classifying Faults in Networks - on - Chip Computing Systems

Brief Project Description: Fault-free design of electronic systems is becoming increasingly difficult due to variations in the silicon manufacturing process, requiring systems to be adaptive to faulty conditions post deployment. Researchers have looked to building brain-inspired computing architectures, based on Spiking Neural Networks (SNN), which aim to mimic the efficient and self-adaptive information processing capabilities of the human brain. The high level of fine-grained parallel processing in the brain is one aspect that enables fault tolerance. Several brain inspired computing approaches have explored the use of Networks-on-Chip (NoC) technology as a mechanism to replicate the parallelism between neurons, such as EMBRACE [1], and the Intelligent Systems Research Centre @ Ulster has recently developed an advance adaptive NoC router for SNNs hardware [2]. However, ultimately such NoC structures are realised using existing silicon manufacturing processes and therefore are susceptible to faults [3]. A key initial task in any fault tolerant system is the monitoring and diagnosing of faults, in particular the ability to sense temporary (SEU, metastability) [4-5] as well as permanent faults (open, short-circuits, stuckat) [6-10]. To advance current NoC-based brain inspired computing paradigms requires the capability to initially detect and diagnose such fault types within the NoC interconnect. A major challenge is the development of a fault diagnosis architecture that can offer adequate fault coverage during real-time operation without incurring substantial cost in terms of area and power consumption.